The present invention relates in general to integrated circuits using field effect transistor (FET) technology, and in particular to techniques for improving reliability and power consumption of such circuits.
Significantly higher degrees of integration have been made possible by the continuous shrinking of dimensions in semiconductor processing. As the FET processing technology moves well into the sub-micron regime, secondary phenomena such as short channel effects and hot carrier degradation become more pronounced. At the same time, there has also been a market driven demand for integrated circuits that operate at more than one power supply levels. Shifting the power supply voltage of a FET circuit from, for example, 3 volts to 5 volts, often exacerbates problems caused by such secondary effects.
Hot electron injection is a secondary effect that degrades circuit performance by causing shifts in the threshold voltage of FETs and/or their transconductance value. Hot electron injection in FETs is typically at its worst case when the drain to source voltage of the transistor is high, and its gate voltage is halfway in between. In digital circuitry such worst case conditions occur only during very short transition periods from one logic level to another. However, analog FET circuitry, and especially CMOS inverters, remain in the maximum hot electron condition a considerable percentage of time. Further, the increased source-to-drain voltage when switching from 3 volt supply voltage to 5 volt supply voltage intensifies the undesired effects.
The capability to integrate more and more active devices onto a single chip has also resulted in substantially larger power consumption and increase in operating temperatures of integrated circuits. In particular, in analog FET circuitry where transistors operate in their linear region for a larger percentage of time, significantly larger amounts of current are dissipated. Power consumption and temperature are also factors that increase proportionally with the power supply voltage.
One way to reduce hot electron injection as well as excessive power consumption and temperature, is to operate FET circuitry with reduced drain-to-source voltages. Thus, when the power supply voltage for a device is switched from, for example, 3 volts to 5 volts, a global on-chip voltage regulator can be used to maintain the lower operating voltages internal to the device. While such a voltage regulator does help to reduce hot electron injection and power consumption, it may not be as effective or practical. For example, a large digital-to-analog converter (DAC) or an analog-to-digital converter (ADC) that uses analog FET inverters, would require an extremely robust voltage regulator to handle all of the transients from all of the circuitry it drives. Such a voltage regulator would be very large, taking valuable silicon area and may still not meet the requirements for larger analog circuits.
Therefore, there is a need for techniques that can help reduce power consumption and temperature as well as secondary effects such as hot electron injection in FET circuitry.